persistent memory

Emerging memory technologies have gotten a couple of big boosts over the past few years, one in the form of Intel’s Optane products, and the other from the migration of CMOS logic to nodes that NOR flash, and now SRAM, cannot practically support. Although these appear to be two very different spheres, a lot of the work that has been undertaken to support Intel’s Optane products (also known as 3D XPoint) will lead to improved use of persistent memories on processors of all kinds: “xPUs”. In this presentation we will review emerging memory technologies and their roles in replacing other on-chip memories, the developments through SNIA and other organizations fostered by Optane, but usable in other aspects of computing, the emergence of new Near/Far Memory paradigms that have spawned interface protocols like CXL and OMI, and the emergence of “Chiplets,” and their potential role in the evolution of persistent processor caches. Learning Objectives: 1) New memories and their impact on computing architecture; 2) Near & Far Memory and how it interacts with new persistent memory technologies; 3) How the adoption of chiplets impacts these changes.

*** Episode in French ***

Nouvel épisode pour ce tech talk qui m'a permis de discuter avec Johan Lombardi, Senior Principale Engineer chez Intel, qui se consacre au projet DAOS (Distributed Asynchronous Object Storage). Un échange qui nous permet de rentrer dans le détail du produit, sa philosophie, ses mécanismes de protection, ses performances et à qui il se destine. Une belle discussion pour en savoir plus sur un projet dédié aux environnements ExaScale demandant des latences très faibles, un nombre important d'IOPS et une très haute bande passante. Merci Johann et bonne écoute.

The SNIA NVMP TWG continues to make significant progress on defining the architecture for interfacing applications to PM. In this talk, we will focus on the important Remote Persistent Memory scenario, and how the NVMP TWG’s programming model applies. Application use of these interfaces, along with fabric support such as RDMA and platform extensions, are part of this, and the talk will describe how the larger ecosystem fits together to support PM as low-latency remote storage.

A variety of persistent memory technologies with DRAM-class performance, known as “memory class storage” or “MCS”, have appeared on the horizon. MCS will change the architecture of future computing systems. These technologies include carbon nanotube memory, phase change memory, magnetic spin memory, and resistive memory, and each has unique characteristics that can complicate systems designed to exploit them. The JEDEC DDR5 NVRAM specification in process intends to bridge the differences between the technologies and provide systems designers with a unified specification for DRAM-class persistent memory. Nantero NRAM is a NVRAM based on carbon nanotube cell structures that provides a DDR4 or DDR5 interface to the system, and provides additional enhancements to yield 20% higher performance at the same clock rate. Learning Objectives: 1) Attendees are exposed to system level advantages of memory class storage devices that operate at DRAM speeds but provide data persistence; 2) JEDEC is working on a new specification to standardize the interface to a variety of NVRAMs which provide memory class storage; 3) Nantero NRAM is a memory class storage device with better than DRAM performance.

Introducing pmemkv, an open-source local key/value store for persistent memory based on PMDK. Written in C/C++, pmemkv provides optimized language bindings for Java, JavaScript, and Ruby. Pmemkv includes multiple storage engines that are tailored for different use-cases. Fast, flexible and bulletproof, pmemkv is an easy way to modify applications to use persistent memory. Learning Objectives: 1) Learn about a local/embedded key-value data store optimized for persistent memory; 2) Learn how cloud applications can easily manage key/value data on persistent platforms; 3) Code samples that demonstrate the ease of use of different language bindings.

As NVDIMMs enter the realm of standard equipment on servers and storage arrays and NVMe is standard equipment for servers and consumer devices alike, what is the actual performance advantage of using NVDIMM over NVMe, or NVMe over SAS or SATA SSDs? First, we’ll review some purely synthetic benchmarks of single devices using different storage technologies and see how they differ. Then, we’ll enter a more real world environment and see what performance gains can be had. One use of NVDIMMs is as a transaction log to allow quick acknowledgement of write operations. In our real-world scenario, we discuss the performance differences of using NVDIMMs, NVMe Flash, or SAS/SATA Flash as the SLOG or “write-cache” for an OpenZFS pool. Learning Objectives: 1) Performance differences between different storage media and storage transports for transactional workloads; 2) Basic overview of OpenZFS and how a SLOG works; 3) Impact of low latency NVDIMM and NVMe storage for application and user latency.

Persistent Memory is getting a lot of attention. SNIA has released a programming standard, NVDIMM makers, with the help of JEDEC, have created standardized hardware to develop & test PM, and chip makers continue to promote upcoming devices, although few are currently available. In this talk two industry analysts, Jim Handy & Tom Coughlin, will provide the state of Persistent Memory and show a realistic roadmap of what the industry can expect to see and when they can expect to see it. The presentation, based on three critical reports covering New Memory Technologies, NVDIMMs, and Intel’s 3D XPoint Memory (also known as Optane) will illustrate the Persistent Memory market, the technologies that vie to play a role, and the critical economic obstacles that continue to impede these technologies’ progress. We will also explore how advanced logic process technologies are likely to cause persistent memories to become a standard ingredient in embedded applications, such as IoT nodes long before they make sense in servers. Learning Objectives: 1) What is the state of emerging memory technologies; 2) What technologies will be used in future NVDIMMS; 3) Emerging memory use in embedded and enterprise applications; 4) What are the costs for making emerging memories.

Have you heard of non-volatile/persistent memory but don’t know how to get started with this disruptive technology? Memory is the new Storage. Next generation storage tiered architectures are evolving with persistent memory and hardware delivering NVDIMMs. Are you a Linux or Windows application developer familiar with C, C++, Java, or Python, keen to develop the next revolutionary application or modify an existing application, but not sure where to start? Do you know what performance and analysis tools can be used to identify optimizations in your app to take advantage of persistent memory? Are you a software, server, or cloud architect that wants to get a jump start on this disruptive technology? This presentation will get you started on the persistent memory solution path. The future is in your hands. The future is now! Learning Objectives: 1) We’ll deliver an introductory understanding of persistent memory, introduce the SNIA Programming Model, Direct Access (DAX) filesystems, and show where persistent memory fits in the storage hierarchy; 2) We’ll provide several options for creating development environments (you don’t need physical modules to get started!); 3) We’ll introduce application programming using the Persistent Memory Developers Kit (PMDK); 4) We’ll introduce and describe how to create and manage Persistent Memory Regions, Namespaces, and Labels; 5) Describe existing analysis tools to identify applications that are good candidates for persistent memory.

Nantero NRAM™ is a new class of memory with the potential to add non-volatility to existing RAM applications. It can be arranged in a crosspoint structure for large memories or a 1T-nR arrangement for smaller faster arrays, in standalone devices or as embedded RAM. NRAM uses carbon nanotubes in a dielectric-free structure to achieve unlimited write endurance. While there are obvious advantages to this class of device, including replacing DRAM in storage devices, there are a number of less obvious changes to how designers approach the data storage hierarchy. Decoupling cache size from battery backup power lets designers rethink performance profiles. Exploitation of various interfaces into the system are examined, from SATA to PCIe to the many options in the DRAM bus. This presentation also explores the growing application space for artificial intelligence, deep learning, and in-memory computing and considers the impact of a high performance non-volatile memory in those use cases. Learning Objectives: 1) Awareness of performance characteristics of a DRAM-class non-volatile memory in crosspoint and 1T-nR configurations; 2) Non-obvious use cases for NRAM; 3) Application of non-volatile memory in AI / deep learning engines.

NVMe over Fabrics is a powerful standard that provides fast access to non-volatile memory devices across fabric interconnects. An emerging NVMe-oF transport is good old TCP/IP. Its benefits are obvious, as it is fast, scalable, well-understood, and extremely simple to deploy. TCP/IP is, after all, the most widely used network protocol of them all, and well known and heavily-implemented in every data center. The major question is how to achieve high performance and low latency with TCP/IP. As most designers know, TCP/IP has pitfalls, such as timeout-based retranmissions and incast. However, performance results are very promising. The NVMe Technical Working Group is building both the standard and its open-source implementation in concert. Its prominent features include data integrity and transport layer security. In practice, NVMe/TCP is an excellent transport for networked flash and complements NVMe/RDMA and NVMe/FC nicely.

Two emerging interconnect efforts, OpenCAPI and Gen-Z, are top-of-mind today in system architecture and storage, including advanced platform support of Persistent Memory. Come hear distinguished leads from each project give an update on the goals, progress, and futures of each. Expect to learn both the differences and commonalities between these potentially symbiotic standards, and how they may enable new platforms and new storage solutions as they move forward.

Our human brain can be modeled as two distinctly different systems: a real time intuition system, and a background reasoning system. As we move into the AI compute era, Emerging Memory technologies play an increasingly important role in overcoming the limitations of DRAM and NAND. The commercialization of Emerging Memory will therefore accelerate our realization of powerful AI systems. In this talk, the speaker will: • Demonstrate the human brain has two distinct systems • Discuss the best fit compute architecture to model each AI system • Articulate how DRAM and NAND are applied to the compute architectures • Identify the key limitations of DRAM and NAND • Present and classify some Emerging Memory alternatives • Discuss the Emerging Memory system enhancements • Identify who is doing what (by when) in the Emerging Memory landscape • Articulate the unique challenges in realizing an AI intuition system • Propose how Emerging Memory may solve some intuition problems • Point to the future of AI systems based on Emerging Memory

The Windows Server 2016 release contains support for Persistent Memory including the introduction of DAX volumes. This presentation will discuss the PM improvemenetns in Windows since this release. We will also review Windows support of the NVML library.

A new class of ultra low latency remote storage is emerging - nonvolatile memory technology can be accessed remotely via high performance storage protocols such as SMB3, over high performance interconnects such as RDMA. A new ecosystem is emerging to "light up" this access end-to-end. This presentation will explore one path to achieve it, with performance data on current approaches, analysis of the overheads, and finally the expectation with simple extensions to well-established protocols.

A tutorial on using the open source persistent memory (PMEM) programming library offered at pmem.io; including examples providing power-fail safety, while storing data on PMEM. Programming examples will zero in on pmem.io’s transactional object store (i.e. “libpmemobj”) library, which is layered on the SNIA NVM Programming Model. The examples covered will demonstrate proper integration techniques, macros, C API, key theory concepts, terminology, and present in depth overview of what the library offers for PMEM programming initiatives. Learning Objectives: 1) Overview of persistent memory programming; 2) Close examination of the transactional object store library (libpmemobj); 3) Code integration walkthrough.

Programming with persistent memory is hard, similar to the type of programming a file system developer does because of the need to write changes out in a way that maintains consistency. Applications must be re-architected to change data stored in two tiers (DRAM and storage) into three tiers (DRAM, pmem and storage). This presentation will review key attributes of persistent memory as well as outline architectural and design considerations for making an application persistent memory aware. This discussion will conclude with examples showing how to modify an application to provide consistency when using persistent memory. Learning Objectives: 1) Introduce how persistent memory differs from DRAM and standard storage for storing application data. 2) Show examples of the architectural considerations for making an application persistent memory aware, 3) Give examples of how to modify an existing application to utilize persistent memory, 4) Discuss the open source Non-Volatile Memory Library (NVML) available on GitHub for use to help with persistent memory programming